wed3dg644v-d1 white electronic designs 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com june 2006 rev. 3 pin front pin back pin front pin back pin back pin back 1v ss 2v ss 51 dq14 52 dq46 95 dq21 96 dq53 3 dq0 4 dq32 53 dq15 54 dq47 97 dq22 98 dq54 5 dq1 6 dq33 55 v ss 56 v ssv 99 dq23 100 dq55 7 dq2 8 dq34 57 nc 58 nc 101 v cc 102 v cc 9 dq3 10 dq35 59 nc 60 nc 103 a6 104 a7 11 v cc 12 v cc voltage key 105 a8 106 ba0 13 dq4 14 dq36 107 v ss 108 v ss 15 dq5 16 dq37 109 a9 110 ba1 17 dq6 18 dq38 61 clk0 62 cke0 111 a10/ap 112 a11 19 dq7 20 dq39 63 v cc 64 v cc 113 v cc 114 v cc 21 v ss 22 v ss 65 ras# 66 cas# 115 dqm2 116 dqm6 23 dqm0 24 dqm4 67 we# 68 *cke1 117 dqm3 118 dqm7 25 dqm1 26 dqm5 69 cs0# 70 *a12 119 v ss 120 vss 27 v cc 28 v cc 71 *cs1# 72 *a13 121 dq24 122 dq56 29 a0 30 a3 73 dnu 74 *ck1 123 dq25 124 dq57 31 a1 32 a4 75 v ss 76 v ss 125 dq26 126 dq58 33 a2 34 a5 77 nc 78 nc 127 dq27 128 dq59 35 v ss 36 v ss 79 nc 80 nc 129 v cc 130 v cc 37 dq8 38 dq40 81 v cc 82 v cc 131 dq28 132 dq60 39 dq9 40 dq41 83 dq16 84 dq48 133 dq29 134 dq61 41 dq10 42 dq42 85 dq17 86 dq49 135 dq30 136 dq62 43 dq11 44 dq43 87 dq18 88 dq50 137 dq31 138 dq63 45 v cc 46 v cc 89 dq19 90 dq51 139 v ss 140 v ss 47 dq12 48 dq44 91 v ss 92 v ss 141 **sda 142 **scl 49 dq13 50 dq45 93 dq20 94 dq52 143 v cc 144 v cc 32mb ? 4mx64 sdram, unbuffered description the wed3dg644v is a 4mx64 synchronous dram module which consists of four 4mx16 sdram components in tsop ii package, and one 2kb eeprom in an 8 pin tsop package for serial presence detect which are mounted on a 144 pin so-dimm multilayer fr4 substrate. * this product is subject to change without notice. note: consult factory for availability of: ? rohs compliant products ? vendor source control options ? industrial temperature option features ? pc100 and pc133 compatible ? burst mode operation ? auto and self refresh capability ? lvttl compatible inputs and outputs ? serial presence detect with eeprom ? fully synchronous: all signals are registered on the positive edge of the system clock ? programmable burst lengths: 1, 2, 4, 8 or full page ? 3.3v 0.3v power supply ? 144 pin so-dimm jedec ? d1: 27.94 (1.10?) pin configurations (front side/back side) pin names * these pins are not used in this module. ** these pins should be nc in the system which does not support spd. a0 ? a11 address input (multiplexed) ba0-1 select bank dq0-63 data input/output clk0 clock input cke0 clock enable input cs0# chip select input ras# row address strobe cas# column address strobe we# write enable dqm0-7 dqm v cc power supply (3.3v) v ss ground *v ref power supply for reference sda serial data i/o scl serial clock dnu do not use nc no connect
wed3dg644v-d1 white electronic designs 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com june 2006 rev. 3 functional block diagram dqm4 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqm1 udqm ldqm ldqm cs# cs# cs# cs0# dqm0 dqm4 dqm2 dqm3 udqm dqm6 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqm5 udqm ldqm dq48 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 ldqm cs# dqm7 udqm serial pd scl ba0 sdram sdram sdram sdram sdram ras# cas# we# cke0 dq n every dqpin of sdram 10 ? v cc v cc two 0.1 uf capacitors per each sdram to all sdrams 47 sda wp sa0 sa1 sa2 ? clk1 10 ? 10pf a0-a11 sdram sdram sdram clk0 sdram sdram 10? 10? notes: 1. all resistor values are 10 ohms unless otherwise speci ed. 2. d1 option does not have series resistors.
wed3dg644v-d1 white electronic designs 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com june 2006 rev. 3 absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v cc supply relative to v ss v cc , v ccq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 4 w short circuit current i os 50 ma note: permanent device damage may occur if ?absolute maximum ratings? are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. parameter symbol min typ max unit note supply voltage v cc 3.0 3.3 3.6 v input high voltage v ih 2.0 3.0 v ccq+0.3 v1 input low voltage v il -0.3 ? 0.8 v 2 output high voltage v oh 2.4 ? ? v i oh = -2ma output low voltage v ol ??0.4vi ol = -2ma input leakage current i li -10 ? 10 a 3 note: 1. v ih (max)= 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min)= -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ccq input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. capacitance t a = 25c, f = 1mhz, v cc = 3.3v, v ref = 1.4v 200mv parameter symbol max unit input capacitance (a0-a12) c in1 25 pf input capacitance (ras#,cas#,we#) c in2 25 pf input capacitance (cke0) c in3 25 pf input capacitance (clk0) c in4 19 pf input capacitance (cs0#) c in5 25 pf input capacitance (dqm0-dqm7) c in6 8pf input capacitance (ba0-ba1) c in7 25 pf data input/output capacitance (dq0-dq63) c out 10 pf recommended dc operating conditions voltage referenced to: v ss = 0v, t a = 0c to +70c
wed3dg644v-d1 white electronic designs 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com june 2006 rev. 3 operating current characteristics (v cc = 3.3v, t a = 0c to +70c) version parameter symbol conditions 133/100 units note operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) i ol = 0ma 300 ma 1 precharge standby current in power down mode i cc2p cke v il (max), t cc = 10ns 4 ma i cc2ps cke & clk v il (max), t cc = 4 precharge standby current in non-power down mode i cc2n cke v ih (min), cs v ih (min), tcc =10ns input signals are charged one time during 20 48 ma i cc2ns cke v ih (min), clk v il (max), t cc = input signals are stable 24 active standby current in power-down mode i cc3p cke v il (max), t cc = 10ns 8 ma i cc3ps cke & clk v il (max), t cc = 8 active standby current in non-power down mode i cc3n cke v ih (min), cs v ih (min), tcc = 10ns input signals are changed one time during 20ns 80 ma i cc3ns cke v ih (min), clk v il (max), tcc = input signals are stable 40 ma operating current (burst mode) i cc4 io = ma page burst 4 banks activated t ccd = 2clk 460 ma 1 refresh current i cc5 t rc t rc (min) 360 ma 2 self refresh current i cc6 cke 0.2v 4 ma notes: 1. measured with outputs open. 2. refresh period is 64ms.
wed3dg644v-d1 white electronic designs 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com june 2006 rev. 3 ac operating test conditions v cc = 3.3v 0.3v, 0 t a 70c parameter value unit ac input levels (v ih /v il ) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time t r /t f = 1/1 ns output timing measurement reference level 1.4 v operating ac parameter (ac operating conditions unless otherwise noted) parameter symbol version unit note 7.5, 10 row active to row active delay t rrd (min) 15 ns 1 ras# to cas# delay t rcd (min) 20 ns 1 row precharge time t rp (min) 20 ns 1 row active time t ras (min) 45 ns 1 t ras (max) 100 us row cycle time t rc (min) 65 ns 1 last data in to row precharge t rdl (min) 2 clk 2 last data in to active delay t dal (min) 2 clk + t rp ? last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 3 number of valid output data cas latency=3 2 ea 4 cas latency=2 1 notes : 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then roundi ng off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop.
wed3dg644v-d1 white electronic designs 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com june 2006 rev. 3 package dimensions for d1 * all dimensions are in millimeters and (inches). 0.99 0.10 (0.039 0.004) 3.20 (0.126) min wedc 27.94 (1.100) max 3.81 (0.150) typ 3.99 (0.157) min 19.99 (0.787) 67.74 (2.667) max 2.01 (0.079) min 32.79 (1.291) 23.19 (0.913) 4.60 (0.181) 1.50 (0.059) 28.24 (1.112) 3.99 (0.157) ordering information for d1 part number clock speed cas latency height* wed3dg644v10d1x-xx 100mhz cl=2 27.94 (1.100?) wed3dg644v7d1x-xx 133mhz cl=2 27.94 (1.100?) wed3dg644v75d1x-xx 133mhz cl=3 27.94 (1.100?) notes: ? consult factory for availability of rohs products. (g = rohs compliant) ? vendor speci c part numbers are used to provide memory components source control. the place holder for this is shown as lower case ?-x? in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali ed sourcing options. (m = micron, s = samsung & consult factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
wed3dg644v-d1 white electronic designs 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com june 2006 rev. 3 part numbering guide wed 3 d g 64 4 v xxx d1 x -x g wedc memory (sdram) sdram gold depth x64 density 3.3 volts clock speed (mhz) package d1 = 144 pin so-dimm industrial temp option (for commercial leave "blank" for industrial add "i") component vendor name (m = micron) (s = samsung) g = rohs compliant (for non-compliant "blank" for rohs add ?g?)
wed3dg644v-d1 white electronic designs 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com june 2006 rev. 3 document title 32mb ? 4mx64 sdram, unbuffered dram die options: ? samsung: k-die ? micron: y14w:g revision history rev # history release date status rev a created 11-15-01 advanced rev 0 changed from advanced to final 9-6-02 final rev 1 updated cap and i dd specs 6-04 final rev 2 2.1 added rohs and lead-free notes 2.2 added vendor source and industrial tem notes 2.3 added part number matrix 1-06 final rev 3 3.1 updated part number guide 3.2 updated ?ordering information? part number 3.3 added dram die options 6-06 final
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